Although applicable in principal to any desired integrated circuits, the present invention and also the problem area on which it is based are explained with regard to integrated memory circuits in silicon technology.
The fabrication of integrated circuits involves patterning layers or layer systems. The same layer or the same layer system is/are generally patterned differently in different successive method steps, and, if appropriate in different regions of the semiconductor substrate. As is known, organic antireflection layers or photosensitive resists are again applied to already patterned regions of the semiconductor structure and are patterned by means of lithography, for example, in order, in a further method step, to perform the desired pattering by transferring the structures into the layering or layer systems. Besides organic antireflection layers, hard masks (also mutlilayered) are also used, which may lead to a multistage patterning process.
As is known, the following problems arise according to the above procedure. Antireflection layers or photoresists flow into the already patterned regions present. The thickness of the antireflection layer or of the photoresist is reduced in the vicinity of the already patterned regions. The reduced thickness produced in the vicinity of the already patterned regions possibly no longer suffices for subsequent process steps (e.g. etches).
On account of an antireflection layer or photoresist running into the already patterned regions, the antireflection layer or the photoresist is much thicker in the structures present and therefore cannot be completely removed, if appropriate.
According to the prior art, when using hard masks (monolayered or multilayered) at the sidewalls of the already patterned regions, it is possible to find different layer thicknesses through to torn-away parts of the hard mask layers. Such different layer thicknesses or torn-away parts of the hard mask layers are typical weak points for the subsequent process steps (e.g. the tearing-away of an SiON layer on a carbon hard mask at an already prepatterned region leads to an attack on the carbon hard mask during for example a subsequent lithography process step, the carbon hard mask that is to be protected by the SiON layer disadvantageously being damaged or destroyed).
Moreover, as already mentioned above, the hard masks used are also deposited in the already patterned regions. Owing to the altered layer thicknesses in and near the already patterned regions and/or the different material properties of the foundations of the already patterned regions, the later removal (stripping) of the hard mask is made more difficult or is not possible.
As is known, it is attempted to solve the abovementioned problems by using the following method. The already patterned regions are filled by a planarizing organic layer. The projecting or excess material is removed again in a so-called recess step. The disadvantages here are as follows. The process sequence has an increased complexity and thereby causes increased costs. Moreover, the use of the planarizing organic layer limits the process temperature for subsequent method steps since the organic filling materials are thermostable only to a limited extent.